期刊


ISSN0925-1030
刊名Analog Integrated Circuits and Signal Processing
参考译名模拟集成电路与信号处理
收藏年代2000～2024



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2024

2024, vol.118, no.1 2024, vol.118, no.2 2024, vol.118, no.3 2024, vol.119, no.1 2024, vol.119, no.2 2024, vol.119, no.3

题名作者出版年年卷期
A 4-D four-wing chaotic system with widely chaotic regions and multiple transient transitionsLi, Lingyun; Chai, Zhijun; Wang, Yunxia20242024, vol.119, no.1
A hybrid ensemble voting-based residual attention network for motor imagery EEG ClassificationJindal, K.; Upadhyay, R.; Singh, H. S.20242024, vol.119, no.1
Design a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency and high-speedArul, A.; Kathirvelu, M.20242024, vol.119, no.1
Design and implementation of high-performance 20-T hybrid full adder circuitKandpal, Jyoti; Tomar, Abhishek20242024, vol.119, no.1
Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logicYamani, Sudha Vani; Ramprasad, M. V. S.; Dinesh, Gundala; Yeshaswila, Eegala Yamini; Teja, Chelluri Ravi; Lokesh, Botta20242024, vol.119, no.1
A design approach for class-AB operational amplifier using the g m /I D methodologyChen, Chen; Cheng, Jinxing; Wang, Hongyi; Fan, Youyou; Wu, Kaikai; Tao, Tao; Wang, Qingbo; Yu, Ai; Wen, Weiwei; Wu, Youpeng; Zhang, Yue20242024, vol.119, no.1
Reliable and ultra-low power approach for designing of logic circuitsUl Haq, Shams; Sharma, Vijay Kumar20242024, vol.119, no.1
Signal dynamic range expansion and power supply voltage reduction for an exponentiation conversion ICNishiyama, Naoya; Matsui, Fumiya; Sano, Yuji20242024, vol.119, no.1
Low voltage high bandwidth FVF current mirror using quasi floating self-cascode output stageDomala, Narsaiah; Sasikala, G.; Raj, Nikhil20242024, vol.119, no.1
Design and simulation of a new current mirror circuit with low power consumption and high performance and output impedanceLi, Yuping; Wang, Haihua; Trik, Mohammad20242024, vol.119, no.1
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