A novel low-power, high-speed carry look ahead adder utilizing 11-T hybrid full adder module based 4:2 compressor unit for low-power applications
参考中译:一种新型低功耗、高速前置加法器，利用基于11-T混合全加器模块的4：2压缩器单元，用于低功耗应用


          

刊名：Analog Integrated Circuits and Signal Processing
作者：Halder, Nimai（Brainware Univ, Barasat, West Bengal, India）
Mukherjee, BiswarupHalder, Nimai（Brainware Univ, Barasat, West Bengal, IndiaBrainware Univ, Barasat, West Bengal, India）
Mukherjee, Biswarup（Brainware Univ, Barasat, West Bengal, India）
刊号：736LB005/IP
ISSN：0925-1030
出版年：2025
年卷期：2025, vol.123, no.2
页码：24-1--24-12
总页数：12
分类号：TN43
关键词：CAD simulation；；CLA；；CMOS；；Compressor；；Gate diffusion input (GDI)；；Hybrid full adder (HFA)
参考中译：CAD模拟;;CLA;;互补金属氧化物;;压缩器;;门扩散输入（LDI）;;混合全加器（HFA）
语种：eng
文摘：In this study, a novel low-power, high-speed hybrid architecture for a 16-bit carry look-ahead adder (CLA) employing 4:2 compressors is proposed. To enhance compressor latency and power efficiency, a new hybrid full adder architecture based on eleven transistors is implemented. The conventional CMOS (CCMOS) architecture of CLAs is hindered by poor latency due to the significant parasitic capacitance presented by higher-order carry generation modules, unlike the ripple carry adder architecture. To mitigate latency issues in the CLA architecture, the design generates odd and even carry bits independently. The proposed 16-bit CLA architecture is simulated using a 45 nm PTM technology model with the Mentor Graphics Tanner EDA tool. Comprehensive simulation-based analyses and comparisons with state-of-the-art methodologies are conducted, focusing on power consumption, delay, and area (transistor count). The proposed design has a power-delay product of 108 femtojoules, which is 53% better than the CCMOS 16-bit CLA architecture.
参考中译：在这项研究中，提出了一种新颖的低功耗、高速混合架构，用于采用4：2压缩器的16位前置进制加法器（CLA）。为了提高压缩器延迟和电源效率，实施了基于十一个晶体管的新混合全加器架构。与波纹进制加法器架构不同，由于更高级的进制进制生成模块呈现的显着寄生电容，导致延迟延迟较低，因此CMA的传统互补性（CCMOS）架构受到阻碍。为了减轻CLA架构中的延迟问题，该设计独立生成奇数和偶数进制位。采用Mentor图形Tanner EDA工具，使用45纳米STM技术模型模拟了拟议的16位CLA架构。进行了全面的基于模拟的分析并与最先进的方法进行了比较，重点关注功耗、延迟和面积（晶体管计数）。提出的设计具有108毫微微焦的功率延迟积，比CCMOS 16位CLA架构好53%。



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